Data Structures for Drivers ddidmalimsparc(9S)
NAME
ddidmalimsparc, ddidmalim - SPARC DMA limits structure
SYNOPSIS
#include
INTERFACE LEVEL
Solaris SPARC DI specific (Solaris SPARC DI). These inter-
faces are obsolete.
DESCRIPTION
This page describes the SPARC version of the ddidmalim
structure. See ddidmalimx86(9S) for a description of the
x86 version of this structure.
A ddidmalim structure describes in a generic fashion the
possible limitations of a device's DMA engine. This informa-
tion is used by the system when it attempts to set up DMA
resources for a device.
STRUCTURE MEMBERS
uintt dlimaddrlo; /* low range of 32 bit
addressing capability */
uintt dlimaddrhi; /* inclusive upper bound of address.
capability */
uintt dlimcntrmax; /* inclusive upper bound of
dma engine address limit * /
uintt dlimburstsizes; /* binary encoded dma burst sizes */
uintt dlimminxfer; /* minimum effective dma xfer size */
uintt dlimdmaspeed; /* average dma data rate (kb/s) */
The dlimaddrlo and dlimaddrhi fields specify the address
range the device's DMA engine can access. The dlimaddrlo
field describes the lower 32-bit boundary of the device's
DMA engine, the dlimaddrhi describes the inclusive upper
32-bit boundary. The system allocates DMA resources in a way
that the address for programming the device's DMA engine
(see ddidmacookie(9S) or ddidmahtoc(9F)) is within this
range. For example, if your device can access the whole 32-
bit address range, you may use [0,0xF]. If your dev-
ice has just a 16-bit address register but will access the
top of the 32-bit address range, then
[0xF0000,0xF] is the right limit.
The dlimcntrmax field describes an inclusive upper bound
for the device's DMA engine address register. This handles a
fairly common case where a portion of the address register
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Data Structures for Drivers ddidmalimsparc(9S)
is only a latch rather than a full register. For example,
the upper 8 bits of a 32-bit address register can be a
latch. This splits the address register into a portion that
acts as a true address register (24 bits) for a 16 Mbyte
segment and a latch (8 bits) to hold a segment number. To
describe these limits, specify 0xF in the
dlimcntrmax structure.
The dlimburstsizes field describes the possible burst sizes
the device's DMA engine can accept. At the time of a DMA
resource request, this element defines the possible DMA
burst cycle sizes that the requester's DMA engine can han-
dle. The format of the data is binary encoding of burst
sizes assumed to be powers of two. That is, if a DMA engine
is capable of doing 1-, 2-, 4-, and 16-byte transfers, the
encoding ix 0x17. If the device is an SBus device and can
take advantage of a 64-bit SBus, the lower 16 bits are used
to specify the burst size for 32-bit transfers and the upper
16 bits are used to specify the burst size for 64-bit
transfers. As the resource request is handled by the system,
the burstsizes value can be modified. Prior to enabling DMA
for the specific device, the driver that owns the DMA engine
should check (using ddidmaburstsizes(9F)) what the allowed
burstsizes have become and program the DMA engine appropri-
ately.
The dlimminxfer field describes the minimum effective DMA
transfer size (in units of bytes). It must be a power of
two. This value specifies the minimum effective granularity
of the DMA engine. It is distinct from dlimburstsizes in
that it describes the minimum amount of access a DMA
transfer will effect. dlimburstsizes describes in what
electrical fashion the DMA engine might perform its
accesses, while dlimminxfer describes the minimum amount of
memory that can be touched by the DMA transfer. As a
resource request is handled by the system, the dlimminxfer
value can be modified contingent upon the presence (and use)
of I/O caches and DMA write buffers in between the DMA
engine and the object that DMA is being performed on. After
DMA resources have been allocated, the resultant minimum
transfer value can be gotten using ddidmadevalign(9F).
The field dlimdmaspeed is the expected average data rate
for the DMA engine (in units of kilobytes per second). Note
that this should not be the maximum, or peak, burst data
rate, but a reasonable guess as to the average throughput.
This field is entirely optional and can be left as zero. Its
intended use is to provide some hints about how much of the
DMA resource this device might need.
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Data Structures for Drivers ddidmalimsparc(9S)
ATRIBUTES
See attributes(5) for descriptions of the following attri-
butes:
ATRIBUTE TYPE ATRIBUTE VALUE
Interface Stability Obsolete
SEE ALSO
ddidmaaddrsetup(9F), ddidmabufsetup(9F),
ddidmaburstsizes(9F), ddidmadevalign(9F),
ddidmahtoc(9F), ddidmasetup(9F), ddidmacookie(9S),
ddidmalimx86(9S), ddidmareq(9S)
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