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The C and C++ Include Header Files

cat -n /usr/include/drm/tegra_drm.h

     1	/* SPDX-License-Identifier: MIT */
     2	/* Copyright (c) 2012-2020 NVIDIA Corporation */
     3	
     4	#ifndef _TEGRA_DRM_H_
     5	#define _TEGRA_DRM_H_
     6	
     7	#include "drm.h"
     8	
     9	#if defined(__cplusplus)
    10	extern "C" {
    11	#endif
    12	
    13	/* Tegra DRM legacy UAPI. Only enabled with STAGING */
    14	
    15	#define DRM_TEGRA_GEM_CREATE_TILED     (1 << 0)
    16	#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
    17	
    18	/**
    19	 * struct drm_tegra_gem_create - parameters for the GEM object creation IOCTL
    20	 */
    21	struct drm_tegra_gem_create {
    22		/**
    23		 * @size:
    24		 *
    25		 * The size, in bytes, of the buffer object to be created.
    26		 */
    27		__u64 size;
    28	
    29		/**
    30		 * @flags:
    31		 *
    32		 * A bitmask of flags that influence the creation of GEM objects:
    33		 *
    34		 * DRM_TEGRA_GEM_CREATE_TILED
    35		 *   Use the 16x16 tiling format for this buffer.
    36		 *
    37		 * DRM_TEGRA_GEM_CREATE_BOTTOM_UP
    38		 *   The buffer has a bottom-up layout.
    39		 */
    40		__u32 flags;
    41	
    42		/**
    43		 * @handle:
    44		 *
    45		 * The handle of the created GEM object. Set by the kernel upon
    46		 * successful completion of the IOCTL.
    47		 */
    48		__u32 handle;
    49	};
    50	
    51	/**
    52	 * struct drm_tegra_gem_mmap - parameters for the GEM mmap IOCTL
    53	 */
    54	struct drm_tegra_gem_mmap {
    55		/**
    56		 * @handle:
    57		 *
    58		 * Handle of the GEM object to obtain an mmap offset for.
    59		 */
    60		__u32 handle;
    61	
    62		/**
    63		 * @pad:
    64		 *
    65		 * Structure padding that may be used in the future. Must be 0.
    66		 */
    67		__u32 pad;
    68	
    69		/**
    70		 * @offset:
    71		 *
    72		 * The mmap offset for the given GEM object. Set by the kernel upon
    73		 * successful completion of the IOCTL.
    74		 */
    75		__u64 offset;
    76	};
    77	
    78	/**
    79	 * struct drm_tegra_syncpt_read - parameters for the read syncpoint IOCTL
    80	 */
    81	struct drm_tegra_syncpt_read {
    82		/**
    83		 * @id:
    84		 *
    85		 * ID of the syncpoint to read the current value from.
    86		 */
    87		__u32 id;
    88	
    89		/**
    90		 * @value:
    91		 *
    92		 * The current syncpoint value. Set by the kernel upon successful
    93		 * completion of the IOCTL.
    94		 */
    95		__u32 value;
    96	};
    97	
    98	/**
    99	 * struct drm_tegra_syncpt_incr - parameters for the increment syncpoint IOCTL
   100	 */
   101	struct drm_tegra_syncpt_incr {
   102		/**
   103		 * @id:
   104		 *
   105		 * ID of the syncpoint to increment.
   106		 */
   107		__u32 id;
   108	
   109		/**
   110		 * @pad:
   111		 *
   112		 * Structure padding that may be used in the future. Must be 0.
   113		 */
   114		__u32 pad;
   115	};
   116	
   117	/**
   118	 * struct drm_tegra_syncpt_wait - parameters for the wait syncpoint IOCTL
   119	 */
   120	struct drm_tegra_syncpt_wait {
   121		/**
   122		 * @id:
   123		 *
   124		 * ID of the syncpoint to wait on.
   125		 */
   126		__u32 id;
   127	
   128		/**
   129		 * @thresh:
   130		 *
   131		 * Threshold value for which to wait.
   132		 */
   133		__u32 thresh;
   134	
   135		/**
   136		 * @timeout:
   137		 *
   138		 * Timeout, in milliseconds, to wait.
   139		 */
   140		__u32 timeout;
   141	
   142		/**
   143		 * @value:
   144		 *
   145		 * The new syncpoint value after the wait. Set by the kernel upon
   146		 * successful completion of the IOCTL.
   147		 */
   148		__u32 value;
   149	};
   150	
   151	#define DRM_TEGRA_NO_TIMEOUT	(0xffffffff)
   152	
   153	/**
   154	 * struct drm_tegra_open_channel - parameters for the open channel IOCTL
   155	 */
   156	struct drm_tegra_open_channel {
   157		/**
   158		 * @client:
   159		 *
   160		 * The client ID for this channel.
   161		 */
   162		__u32 client;
   163	
   164		/**
   165		 * @pad:
   166		 *
   167		 * Structure padding that may be used in the future. Must be 0.
   168		 */
   169		__u32 pad;
   170	
   171		/**
   172		 * @context:
   173		 *
   174		 * The application context of this channel. Set by the kernel upon
   175		 * successful completion of the IOCTL. This context needs to be passed
   176		 * to the DRM_TEGRA_CHANNEL_CLOSE or the DRM_TEGRA_SUBMIT IOCTLs.
   177		 */
   178		__u64 context;
   179	};
   180	
   181	/**
   182	 * struct drm_tegra_close_channel - parameters for the close channel IOCTL
   183	 */
   184	struct drm_tegra_close_channel {
   185		/**
   186		 * @context:
   187		 *
   188		 * The application context of this channel. This is obtained from the
   189		 * DRM_TEGRA_OPEN_CHANNEL IOCTL.
   190		 */
   191		__u64 context;
   192	};
   193	
   194	/**
   195	 * struct drm_tegra_get_syncpt - parameters for the get syncpoint IOCTL
   196	 */
   197	struct drm_tegra_get_syncpt {
   198		/**
   199		 * @context:
   200		 *
   201		 * The application context identifying the channel for which to obtain
   202		 * the syncpoint ID.
   203		 */
   204		__u64 context;
   205	
   206		/**
   207		 * @index:
   208		 *
   209		 * Index of the client syncpoint for which to obtain the ID.
   210		 */
   211		__u32 index;
   212	
   213		/**
   214		 * @id:
   215		 *
   216		 * The ID of the given syncpoint. Set by the kernel upon successful
   217		 * completion of the IOCTL.
   218		 */
   219		__u32 id;
   220	};
   221	
   222	/**
   223	 * struct drm_tegra_get_syncpt_base - parameters for the get wait base IOCTL
   224	 */
   225	struct drm_tegra_get_syncpt_base {
   226		/**
   227		 * @context:
   228		 *
   229		 * The application context identifying for which channel to obtain the
   230		 * wait base.
   231		 */
   232		__u64 context;
   233	
   234		/**
   235		 * @syncpt:
   236		 *
   237		 * ID of the syncpoint for which to obtain the wait base.
   238		 */
   239		__u32 syncpt;
   240	
   241		/**
   242		 * @id:
   243		 *
   244		 * The ID of the wait base corresponding to the client syncpoint. Set
   245		 * by the kernel upon successful completion of the IOCTL.
   246		 */
   247		__u32 id;
   248	};
   249	
   250	/**
   251	 * struct drm_tegra_syncpt - syncpoint increment operation
   252	 */
   253	struct drm_tegra_syncpt {
   254		/**
   255		 * @id:
   256		 *
   257		 * ID of the syncpoint to operate on.
   258		 */
   259		__u32 id;
   260	
   261		/**
   262		 * @incrs:
   263		 *
   264		 * Number of increments to perform for the syncpoint.
   265		 */
   266		__u32 incrs;
   267	};
   268	
   269	/**
   270	 * struct drm_tegra_cmdbuf - structure describing a command buffer
   271	 */
   272	struct drm_tegra_cmdbuf {
   273		/**
   274		 * @handle:
   275		 *
   276		 * Handle to a GEM object containing the command buffer.
   277		 */
   278		__u32 handle;
   279	
   280		/**
   281		 * @offset:
   282		 *
   283		 * Offset, in bytes, into the GEM object identified by @handle at
   284		 * which the command buffer starts.
   285		 */
   286		__u32 offset;
   287	
   288		/**
   289		 * @words:
   290		 *
   291		 * Number of 32-bit words in this command buffer.
   292		 */
   293		__u32 words;
   294	
   295		/**
   296		 * @pad:
   297		 *
   298		 * Structure padding that may be used in the future. Must be 0.
   299		 */
   300		__u32 pad;
   301	};
   302	
   303	/**
   304	 * struct drm_tegra_reloc - GEM object relocation structure
   305	 */
   306	struct drm_tegra_reloc {
   307		struct {
   308			/**
   309			 * @cmdbuf.handle:
   310			 *
   311			 * Handle to the GEM object containing the command buffer for
   312			 * which to perform this GEM object relocation.
   313			 */
   314			__u32 handle;
   315	
   316			/**
   317			 * @cmdbuf.offset:
   318			 *
   319			 * Offset, in bytes, into the command buffer at which to
   320			 * insert the relocated address.
   321			 */
   322			__u32 offset;
   323		} cmdbuf;
   324		struct {
   325			/**
   326			 * @target.handle:
   327			 *
   328			 * Handle to the GEM object to be relocated.
   329			 */
   330			__u32 handle;
   331	
   332			/**
   333			 * @target.offset:
   334			 *
   335			 * Offset, in bytes, into the target GEM object at which the
   336			 * relocated data starts.
   337			 */
   338			__u32 offset;
   339		} target;
   340	
   341		/**
   342		 * @shift:
   343		 *
   344		 * The number of bits by which to shift relocated addresses.
   345		 */
   346		__u32 shift;
   347	
   348		/**
   349		 * @pad:
   350		 *
   351		 * Structure padding that may be used in the future. Must be 0.
   352		 */
   353		__u32 pad;
   354	};
   355	
   356	/**
   357	 * struct drm_tegra_waitchk - wait check structure
   358	 */
   359	struct drm_tegra_waitchk {
   360		/**
   361		 * @handle:
   362		 *
   363		 * Handle to the GEM object containing a command stream on which to
   364		 * perform the wait check.
   365		 */
   366		__u32 handle;
   367	
   368		/**
   369		 * @offset:
   370		 *
   371		 * Offset, in bytes, of the location in the command stream to perform
   372		 * the wait check on.
   373		 */
   374		__u32 offset;
   375	
   376		/**
   377		 * @syncpt:
   378		 *
   379		 * ID of the syncpoint to wait check.
   380		 */
   381		__u32 syncpt;
   382	
   383		/**
   384		 * @thresh:
   385		 *
   386		 * Threshold value for which to check.
   387		 */
   388		__u32 thresh;
   389	};
   390	
   391	/**
   392	 * struct drm_tegra_submit - job submission structure
   393	 */
   394	struct drm_tegra_submit {
   395		/**
   396		 * @context:
   397		 *
   398		 * The application context identifying the channel to use for the
   399		 * execution of this job.
   400		 */
   401		__u64 context;
   402	
   403		/**
   404		 * @num_syncpts:
   405		 *
   406		 * The number of syncpoints operated on by this job. This defines the
   407		 * length of the array pointed to by @syncpts.
   408		 */
   409		__u32 num_syncpts;
   410	
   411		/**
   412		 * @num_cmdbufs:
   413		 *
   414		 * The number of command buffers to execute as part of this job. This
   415		 * defines the length of the array pointed to by @cmdbufs.
   416		 */
   417		__u32 num_cmdbufs;
   418	
   419		/**
   420		 * @num_relocs:
   421		 *
   422		 * The number of relocations to perform before executing this job.
   423		 * This defines the length of the array pointed to by @relocs.
   424		 */
   425		__u32 num_relocs;
   426	
   427		/**
   428		 * @num_waitchks:
   429		 *
   430		 * The number of wait checks to perform as part of this job. This
   431		 * defines the length of the array pointed to by @waitchks.
   432		 */
   433		__u32 num_waitchks;
   434	
   435		/**
   436		 * @waitchk_mask:
   437		 *
   438		 * Bitmask of valid wait checks.
   439		 */
   440		__u32 waitchk_mask;
   441	
   442		/**
   443		 * @timeout:
   444		 *
   445		 * Timeout, in milliseconds, before this job is cancelled.
   446		 */
   447		__u32 timeout;
   448	
   449		/**
   450		 * @syncpts:
   451		 *
   452		 * A pointer to an array of &struct drm_tegra_syncpt structures that
   453		 * specify the syncpoint operations performed as part of this job.
   454		 * The number of elements in the array must be equal to the value
   455		 * given by @num_syncpts.
   456		 */
   457		__u64 syncpts;
   458	
   459		/**
   460		 * @cmdbufs:
   461		 *
   462		 * A pointer to an array of &struct drm_tegra_cmdbuf structures that
   463		 * define the command buffers to execute as part of this job. The
   464		 * number of elements in the array must be equal to the value given
   465		 * by @num_syncpts.
   466		 */
   467		__u64 cmdbufs;
   468	
   469		/**
   470		 * @relocs:
   471		 *
   472		 * A pointer to an array of &struct drm_tegra_reloc structures that
   473		 * specify the relocations that need to be performed before executing
   474		 * this job. The number of elements in the array must be equal to the
   475		 * value given by @num_relocs.
   476		 */
   477		__u64 relocs;
   478	
   479		/**
   480		 * @waitchks:
   481		 *
   482		 * A pointer to an array of &struct drm_tegra_waitchk structures that
   483		 * specify the wait checks to be performed while executing this job.
   484		 * The number of elements in the array must be equal to the value
   485		 * given by @num_waitchks.
   486		 */
   487		__u64 waitchks;
   488	
   489		/**
   490		 * @fence:
   491		 *
   492		 * The threshold of the syncpoint associated with this job after it
   493		 * has been completed. Set by the kernel upon successful completion of
   494		 * the IOCTL. This can be used with the DRM_TEGRA_SYNCPT_WAIT IOCTL to
   495		 * wait for this job to be finished.
   496		 */
   497		__u32 fence;
   498	
   499		/**
   500		 * @reserved:
   501		 *
   502		 * This field is reserved for future use. Must be 0.
   503		 */
   504		__u32 reserved[5];
   505	};
   506	
   507	#define DRM_TEGRA_GEM_TILING_MODE_PITCH 0
   508	#define DRM_TEGRA_GEM_TILING_MODE_TILED 1
   509	#define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2
   510	
   511	/**
   512	 * struct drm_tegra_gem_set_tiling - parameters for the set tiling IOCTL
   513	 */
   514	struct drm_tegra_gem_set_tiling {
   515		/**
   516		 * @handle:
   517		 *
   518		 * Handle to the GEM object for which to set the tiling parameters.
   519		 */
   520		__u32 handle;
   521	
   522		/**
   523		 * @mode:
   524		 *
   525		 * The tiling mode to set. Must be one of:
   526		 *
   527		 * DRM_TEGRA_GEM_TILING_MODE_PITCH
   528		 *   pitch linear format
   529		 *
   530		 * DRM_TEGRA_GEM_TILING_MODE_TILED
   531		 *   16x16 tiling format
   532		 *
   533		 * DRM_TEGRA_GEM_TILING_MODE_BLOCK
   534		 *   16Bx2 tiling format
   535		 */
   536		__u32 mode;
   537	
   538		/**
   539		 * @value:
   540		 *
   541		 * The value to set for the tiling mode parameter.
   542		 */
   543		__u32 value;
   544	
   545		/**
   546		 * @pad:
   547		 *
   548		 * Structure padding that may be used in the future. Must be 0.
   549		 */
   550		__u32 pad;
   551	};
   552	
   553	/**
   554	 * struct drm_tegra_gem_get_tiling - parameters for the get tiling IOCTL
   555	 */
   556	struct drm_tegra_gem_get_tiling {
   557		/**
   558		 * @handle:
   559		 *
   560		 * Handle to the GEM object for which to query the tiling parameters.
   561		 */
   562		__u32 handle;
   563	
   564		/**
   565		 * @mode:
   566		 *
   567		 * The tiling mode currently associated with the GEM object. Set by
   568		 * the kernel upon successful completion of the IOCTL.
   569		 */
   570		__u32 mode;
   571	
   572		/**
   573		 * @value:
   574		 *
   575		 * The tiling mode parameter currently associated with the GEM object.
   576		 * Set by the kernel upon successful completion of the IOCTL.
   577		 */
   578		__u32 value;
   579	
   580		/**
   581		 * @pad:
   582		 *
   583		 * Structure padding that may be used in the future. Must be 0.
   584		 */
   585		__u32 pad;
   586	};
   587	
   588	#define DRM_TEGRA_GEM_BOTTOM_UP		(1 << 0)
   589	#define DRM_TEGRA_GEM_FLAGS		(DRM_TEGRA_GEM_BOTTOM_UP)
   590	
   591	/**
   592	 * struct drm_tegra_gem_set_flags - parameters for the set flags IOCTL
   593	 */
   594	struct drm_tegra_gem_set_flags {
   595		/**
   596		 * @handle:
   597		 *
   598		 * Handle to the GEM object for which to set the flags.
   599		 */
   600		__u32 handle;
   601	
   602		/**
   603		 * @flags:
   604		 *
   605		 * The flags to set for the GEM object.
   606		 */
   607		__u32 flags;
   608	};
   609	
   610	/**
   611	 * struct drm_tegra_gem_get_flags - parameters for the get flags IOCTL
   612	 */
   613	struct drm_tegra_gem_get_flags {
   614		/**
   615		 * @handle:
   616		 *
   617		 * Handle to the GEM object for which to query the flags.
   618		 */
   619		__u32 handle;
   620	
   621		/**
   622		 * @flags:
   623		 *
   624		 * The flags currently associated with the GEM object. Set by the
   625		 * kernel upon successful completion of the IOCTL.
   626		 */
   627		__u32 flags;
   628	};
   629	
   630	#define DRM_TEGRA_GEM_CREATE		0x00
   631	#define DRM_TEGRA_GEM_MMAP		0x01
   632	#define DRM_TEGRA_SYNCPT_READ		0x02
   633	#define DRM_TEGRA_SYNCPT_INCR		0x03
   634	#define DRM_TEGRA_SYNCPT_WAIT		0x04
   635	#define DRM_TEGRA_OPEN_CHANNEL	        0x05
   636	#define DRM_TEGRA_CLOSE_CHANNEL	        0x06
   637	#define DRM_TEGRA_GET_SYNCPT		0x07
   638	#define DRM_TEGRA_SUBMIT		0x08
   639	#define DRM_TEGRA_GET_SYNCPT_BASE	0x09
   640	#define DRM_TEGRA_GEM_SET_TILING	0x0a
   641	#define DRM_TEGRA_GEM_GET_TILING	0x0b
   642	#define DRM_TEGRA_GEM_SET_FLAGS		0x0c
   643	#define DRM_TEGRA_GEM_GET_FLAGS		0x0d
   644	
   645	#define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create)
   646	#define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap)
   647	#define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read)
   648	#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
   649	#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
   650	#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
   651	#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_close_channel)
   652	#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
   653	#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
   654	#define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base)
   655	#define DRM_IOCTL_TEGRA_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_TILING, struct drm_tegra_gem_set_tiling)
   656	#define DRM_IOCTL_TEGRA_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_TILING, struct drm_tegra_gem_get_tiling)
   657	#define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags)
   658	#define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags)
   659	
   660	/* New Tegra DRM UAPI */
   661	
   662	/*
   663	 * Reported by the driver in the `capabilities` field.
   664	 *
   665	 * DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT: If set, the engine is cache coherent
   666	 * with regard to the system memory.
   667	 */
   668	#define DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT (1 << 0)
   669	
   670	struct drm_tegra_channel_open {
   671		/**
   672		 * @host1x_class: [in]
   673		 *
   674		 * Host1x class of the engine that will be programmed using this
   675		 * channel.
   676		 */
   677		__u32 host1x_class;
   678	
   679		/**
   680		 * @flags: [in]
   681		 *
   682		 * Flags.
   683		 */
   684		__u32 flags;
   685	
   686		/**
   687		 * @context: [out]
   688		 *
   689		 * Opaque identifier corresponding to the opened channel.
   690		 */
   691		__u32 context;
   692	
   693		/**
   694		 * @version: [out]
   695		 *
   696		 * Version of the engine hardware. This can be used by userspace
   697		 * to determine how the engine needs to be programmed.
   698		 */
   699		__u32 version;
   700	
   701		/**
   702		 * @capabilities: [out]
   703		 *
   704		 * Flags describing the hardware capabilities.
   705		 */
   706		__u32 capabilities;
   707		__u32 padding;
   708	};
   709	
   710	struct drm_tegra_channel_close {
   711		/**
   712		 * @context: [in]
   713		 *
   714		 * Identifier of the channel to close.
   715		 */
   716		__u32 context;
   717		__u32 padding;
   718	};
   719	
   720	/*
   721	 * Mapping flags that can be used to influence how the mapping is created.
   722	 *
   723	 * DRM_TEGRA_CHANNEL_MAP_READ: create mapping that allows HW read access
   724	 * DRM_TEGRA_CHANNEL_MAP_WRITE: create mapping that allows HW write access
   725	 */
   726	#define DRM_TEGRA_CHANNEL_MAP_READ  (1 << 0)
   727	#define DRM_TEGRA_CHANNEL_MAP_WRITE (1 << 1)
   728	#define DRM_TEGRA_CHANNEL_MAP_READ_WRITE (DRM_TEGRA_CHANNEL_MAP_READ | \
   729						  DRM_TEGRA_CHANNEL_MAP_WRITE)
   730	
   731	struct drm_tegra_channel_map {
   732		/**
   733		 * @context: [in]
   734		 *
   735		 * Identifier of the channel to which make memory available for.
   736		 */
   737		__u32 context;
   738	
   739		/**
   740		 * @handle: [in]
   741		 *
   742		 * GEM handle of the memory to map.
   743		 */
   744		__u32 handle;
   745	
   746		/**
   747		 * @flags: [in]
   748		 *
   749		 * Flags.
   750		 */
   751		__u32 flags;
   752	
   753		/**
   754		 * @mapping: [out]
   755		 *
   756		 * Identifier corresponding to the mapping, to be used for
   757		 * relocations or unmapping later.
   758		 */
   759		__u32 mapping;
   760	};
   761	
   762	struct drm_tegra_channel_unmap {
   763		/**
   764		 * @context: [in]
   765		 *
   766		 * Channel identifier of the channel to unmap memory from.
   767		 */
   768		__u32 context;
   769	
   770		/**
   771		 * @mapping: [in]
   772		 *
   773		 * Mapping identifier of the memory mapping to unmap.
   774		 */
   775		__u32 mapping;
   776	};
   777	
   778	/* Submission */
   779	
   780	/**
   781	 * Specify that bit 39 of the patched-in address should be set to switch
   782	 * swizzling between Tegra and non-Tegra sector layout on systems that store
   783	 * surfaces in system memory in non-Tegra sector layout.
   784	 */
   785	#define DRM_TEGRA_SUBMIT_RELOC_SECTOR_LAYOUT (1 << 0)
   786	
   787	struct drm_tegra_submit_buf {
   788		/**
   789		 * @mapping: [in]
   790		 *
   791		 * Identifier of the mapping to use in the submission.
   792		 */
   793		__u32 mapping;
   794	
   795		/**
   796		 * @flags: [in]
   797		 *
   798		 * Flags.
   799		 */
   800		__u32 flags;
   801	
   802		/**
   803		 * Information for relocation patching.
   804		 */
   805		struct {
   806			/**
   807			 * @target_offset: [in]
   808			 *
   809			 * Offset from the start of the mapping of the data whose
   810			 * address is to be patched into the gather.
   811			 */
   812			__u64 target_offset;
   813	
   814			/**
   815			 * @gather_offset_words: [in]
   816			 *
   817			 * Offset in words from the start of the gather data to
   818			 * where the address should be patched into.
   819			 */
   820			__u32 gather_offset_words;
   821	
   822			/**
   823			 * @shift: [in]
   824			 *
   825			 * Number of bits the address should be shifted right before
   826			 * patching in.
   827			 */
   828			__u32 shift;
   829		} reloc;
   830	};
   831	
   832	/**
   833	 * Execute `words` words of Host1x opcodes specified in the `gather_data_ptr`
   834	 * buffer. Each GATHER_UPTR command uses successive words from the buffer.
   835	 */
   836	#define DRM_TEGRA_SUBMIT_CMD_GATHER_UPTR		0
   837	/**
   838	 * Wait for a syncpoint to reach a value before continuing with further
   839	 * commands.
   840	 */
   841	#define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT		1
   842	/**
   843	 * Wait for a syncpoint to reach a value before continuing with further
   844	 * commands. The threshold is calculated relative to the start of the job.
   845	 */
   846	#define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT_RELATIVE	2
   847	
   848	struct drm_tegra_submit_cmd_gather_uptr {
   849		__u32 words;
   850		__u32 reserved[3];
   851	};
   852	
   853	struct drm_tegra_submit_cmd_wait_syncpt {
   854		__u32 id;
   855		__u32 value;
   856		__u32 reserved[2];
   857	};
   858	
   859	struct drm_tegra_submit_cmd {
   860		/**
   861		 * @type: [in]
   862		 *
   863		 * Command type to execute. One of the DRM_TEGRA_SUBMIT_CMD*
   864		 * defines.
   865		 */
   866		__u32 type;
   867	
   868		/**
   869		 * @flags: [in]
   870		 *
   871		 * Flags.
   872		 */
   873		__u32 flags;
   874	
   875		union {
   876			struct drm_tegra_submit_cmd_gather_uptr gather_uptr;
   877			struct drm_tegra_submit_cmd_wait_syncpt wait_syncpt;
   878			__u32 reserved[4];
   879		};
   880	};
   881	
   882	struct drm_tegra_submit_syncpt {
   883		/**
   884		 * @id: [in]
   885		 *
   886		 * ID of the syncpoint that the job will increment.
   887		 */
   888		__u32 id;
   889	
   890		/**
   891		 * @flags: [in]
   892		 *
   893		 * Flags.
   894		 */
   895		__u32 flags;
   896	
   897		/**
   898		 * @increments: [in]
   899		 *
   900		 * Number of times the job will increment this syncpoint.
   901		 */
   902		__u32 increments;
   903	
   904		/**
   905		 * @value: [out]
   906		 *
   907		 * Value the syncpoint will have once the job has completed all
   908		 * its specified syncpoint increments.
   909		 *
   910		 * Note that the kernel may increment the syncpoint before or after
   911		 * the job. These increments are not reflected in this field.
   912		 *
   913		 * If the job hangs or times out, not all of the increments may
   914		 * get executed.
   915		 */
   916		__u32 value;
   917	};
   918	
   919	struct drm_tegra_channel_submit {
   920		/**
   921		 * @context: [in]
   922		 *
   923		 * Identifier of the channel to submit this job to.
   924		 */
   925		__u32 context;
   926	
   927		/**
   928		 * @num_bufs: [in]
   929		 *
   930		 * Number of elements in the `bufs_ptr` array.
   931		 */
   932		__u32 num_bufs;
   933	
   934		/**
   935		 * @num_cmds: [in]
   936		 *
   937		 * Number of elements in the `cmds_ptr` array.
   938		 */
   939		__u32 num_cmds;
   940	
   941		/**
   942		 * @gather_data_words: [in]
   943		 *
   944		 * Number of 32-bit words in the `gather_data_ptr` array.
   945		 */
   946		__u32 gather_data_words;
   947	
   948		/**
   949		 * @bufs_ptr: [in]
   950		 *
   951		 * Pointer to an array of drm_tegra_submit_buf structures.
   952		 */
   953		__u64 bufs_ptr;
   954	
   955		/**
   956		 * @cmds_ptr: [in]
   957		 *
   958		 * Pointer to an array of drm_tegra_submit_cmd structures.
   959		 */
   960		__u64 cmds_ptr;
   961	
   962		/**
   963		 * @gather_data_ptr: [in]
   964		 *
   965		 * Pointer to an array of Host1x opcodes to be used by GATHER_UPTR
   966		 * commands.
   967		 */
   968		__u64 gather_data_ptr;
   969	
   970		/**
   971		 * @syncobj_in: [in]
   972		 *
   973		 * Handle for DRM syncobj that will be waited before submission.
   974		 * Ignored if zero.
   975		 */
   976		__u32 syncobj_in;
   977	
   978		/**
   979		 * @syncobj_out: [in]
   980		 *
   981		 * Handle for DRM syncobj that will have its fence replaced with
   982		 * the job's completion fence. Ignored if zero.
   983		 */
   984		__u32 syncobj_out;
   985	
   986		/**
   987		 * @syncpt_incr: [in,out]
   988		 *
   989		 * Information about the syncpoint the job will increment.
   990		 */
   991		struct drm_tegra_submit_syncpt syncpt;
   992	};
   993	
   994	struct drm_tegra_syncpoint_allocate {
   995		/**
   996		 * @id: [out]
   997		 *
   998		 * ID of allocated syncpoint.
   999		 */
  1000		__u32 id;
  1001		__u32 padding;
  1002	};
  1003	
  1004	struct drm_tegra_syncpoint_free {
  1005		/**
  1006		 * @id: [in]
  1007		 *
  1008		 * ID of syncpoint to free.
  1009		 */
  1010		__u32 id;
  1011		__u32 padding;
  1012	};
  1013	
  1014	struct drm_tegra_syncpoint_wait {
  1015		/**
  1016		 * @timeout: [in]
  1017		 *
  1018		 * Absolute timestamp at which the wait will time out.
  1019		 */
  1020		__s64 timeout_ns;
  1021	
  1022		/**
  1023		 * @id: [in]
  1024		 *
  1025		 * ID of syncpoint to wait on.
  1026		 */
  1027		__u32 id;
  1028	
  1029		/**
  1030		 * @threshold: [in]
  1031		 *
  1032		 * Threshold to wait for.
  1033		 */
  1034		__u32 threshold;
  1035	
  1036		/**
  1037		 * @value: [out]
  1038		 *
  1039		 * Value of the syncpoint upon wait completion.
  1040		 */
  1041		__u32 value;
  1042	
  1043		__u32 padding;
  1044	};
  1045	
  1046	#define DRM_IOCTL_TEGRA_CHANNEL_OPEN DRM_IOWR(DRM_COMMAND_BASE + 0x10, struct drm_tegra_channel_open)
  1047	#define DRM_IOCTL_TEGRA_CHANNEL_CLOSE DRM_IOWR(DRM_COMMAND_BASE + 0x11, struct drm_tegra_channel_close)
  1048	#define DRM_IOCTL_TEGRA_CHANNEL_MAP DRM_IOWR(DRM_COMMAND_BASE + 0x12, struct drm_tegra_channel_map)
  1049	#define DRM_IOCTL_TEGRA_CHANNEL_UNMAP DRM_IOWR(DRM_COMMAND_BASE + 0x13, struct drm_tegra_channel_unmap)
  1050	#define DRM_IOCTL_TEGRA_CHANNEL_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + 0x14, struct drm_tegra_channel_submit)
  1051	
  1052	#define DRM_IOCTL_TEGRA_SYNCPOINT_ALLOCATE DRM_IOWR(DRM_COMMAND_BASE + 0x20, struct drm_tegra_syncpoint_allocate)
  1053	#define DRM_IOCTL_TEGRA_SYNCPOINT_FREE DRM_IOWR(DRM_COMMAND_BASE + 0x21, struct drm_tegra_syncpoint_free)
  1054	#define DRM_IOCTL_TEGRA_SYNCPOINT_WAIT DRM_IOWR(DRM_COMMAND_BASE + 0x22, struct drm_tegra_syncpoint_wait)
  1055	
  1056	#if defined(__cplusplus)
  1057	}
  1058	#endif
  1059	
  1060	#endif