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The C and C++ Include Header Files

cat -n /usr/include/linux/fpga-dfl.h

     1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
     2	/*
     3	 * Header File for FPGA DFL User API
     4	 *
     5	 * Copyright (C) 2017-2018 Intel Corporation, Inc.
     6	 *
     7	 * Authors:
     8	 *   Kang Luwei <luwei.kang@intel.com>
     9	 *   Zhang Yi <yi.z.zhang@intel.com>
    10	 *   Wu Hao <hao.wu@intel.com>
    11	 *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
    12	 */
    13	
    14	#ifndef _LINUX_FPGA_DFL_H
    15	#define _LINUX_FPGA_DFL_H
    16	
    17	#include <linux/types.h>
    18	#include <linux/ioctl.h>
    19	
    20	#define DFL_FPGA_API_VERSION 0
    21	
    22	/*
    23	 * The IOCTL interface for DFL based FPGA is designed for extensibility by
    24	 * embedding the structure length (argsz) and flags into structures passed
    25	 * between kernel and userspace. This design referenced the VFIO IOCTL
    26	 * interface (include/uapi/linux/vfio.h).
    27	 */
    28	
    29	#define DFL_FPGA_MAGIC 0xB6
    30	
    31	#define DFL_FPGA_BASE 0
    32	#define DFL_PORT_BASE 0x40
    33	#define DFL_FME_BASE 0x80
    34	
    35	/* Common IOCTLs for both FME and AFU file descriptor */
    36	
    37	/**
    38	 * DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0)
    39	 *
    40	 * Report the version of the driver API.
    41	 * Return: Driver API Version.
    42	 */
    43	
    44	#define DFL_FPGA_GET_API_VERSION	_IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0)
    45	
    46	/**
    47	 * DFL_FPGA_CHECK_EXTENSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1)
    48	 *
    49	 * Check whether an extension is supported.
    50	 * Return: 0 if not supported, otherwise the extension is supported.
    51	 */
    52	
    53	#define DFL_FPGA_CHECK_EXTENSION	_IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1)
    54	
    55	/* IOCTLs for AFU file descriptor */
    56	
    57	/**
    58	 * DFL_FPGA_PORT_RESET - _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0)
    59	 *
    60	 * Reset the FPGA Port and its AFU. No parameters are supported.
    61	 * Userspace can do Port reset at any time, e.g. during DMA or PR. But
    62	 * it should never cause any system level issue, only functional failure
    63	 * (e.g. DMA or PR operation failure) and be recoverable from the failure.
    64	 * Return: 0 on success, -errno of failure
    65	 */
    66	
    67	#define DFL_FPGA_PORT_RESET		_IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0)
    68	
    69	/**
    70	 * DFL_FPGA_PORT_GET_INFO - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1,
    71	 *						struct dfl_fpga_port_info)
    72	 *
    73	 * Retrieve information about the fpga port.
    74	 * Driver fills the info in provided struct dfl_fpga_port_info.
    75	 * Return: 0 on success, -errno on failure.
    76	 */
    77	struct dfl_fpga_port_info {
    78		/* Input */
    79		__u32 argsz;		/* Structure length */
    80		/* Output */
    81		__u32 flags;		/* Zero for now */
    82		__u32 num_regions;	/* The number of supported regions */
    83		__u32 num_umsgs;	/* The number of allocated umsgs */
    84	};
    85	
    86	#define DFL_FPGA_PORT_GET_INFO		_IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1)
    87	
    88	/**
    89	 * FPGA_PORT_GET_REGION_INFO - _IOWR(FPGA_MAGIC, PORT_BASE + 2,
    90	 *					struct dfl_fpga_port_region_info)
    91	 *
    92	 * Retrieve information about a device memory region.
    93	 * Caller provides struct dfl_fpga_port_region_info with index value set.
    94	 * Driver returns the region info in other fields.
    95	 * Return: 0 on success, -errno on failure.
    96	 */
    97	struct dfl_fpga_port_region_info {
    98		/* input */
    99		__u32 argsz;		/* Structure length */
   100		/* Output */
   101		__u32 flags;		/* Access permission */
   102	#define DFL_PORT_REGION_READ	(1 << 0)	/* Region is readable */
   103	#define DFL_PORT_REGION_WRITE	(1 << 1)	/* Region is writable */
   104	#define DFL_PORT_REGION_MMAP	(1 << 2)	/* Can be mmaped to userspace */
   105		/* Input */
   106		__u32 index;		/* Region index */
   107	#define DFL_PORT_REGION_INDEX_AFU	0	/* AFU */
   108	#define DFL_PORT_REGION_INDEX_STP	1	/* Signal Tap */
   109		__u32 padding;
   110		/* Output */
   111		__u64 size;		/* Region size (bytes) */
   112		__u64 offset;		/* Region offset from start of device fd */
   113	};
   114	
   115	#define DFL_FPGA_PORT_GET_REGION_INFO	_IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 2)
   116	
   117	/**
   118	 * DFL_FPGA_PORT_DMA_MAP - _IOWR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 3,
   119	 *						struct dfl_fpga_port_dma_map)
   120	 *
   121	 * Map the dma memory per user_addr and length which are provided by caller.
   122	 * Driver fills the iova in provided struct afu_port_dma_map.
   123	 * This interface only accepts page-size aligned user memory for dma mapping.
   124	 * Return: 0 on success, -errno on failure.
   125	 */
   126	struct dfl_fpga_port_dma_map {
   127		/* Input */
   128		__u32 argsz;		/* Structure length */
   129		__u32 flags;		/* Zero for now */
   130		__u64 user_addr;        /* Process virtual address */
   131		__u64 length;           /* Length of mapping (bytes)*/
   132		/* Output */
   133		__u64 iova;             /* IO virtual address */
   134	};
   135	
   136	#define DFL_FPGA_PORT_DMA_MAP		_IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 3)
   137	
   138	/**
   139	 * DFL_FPGA_PORT_DMA_UNMAP - _IOW(FPGA_MAGIC, PORT_BASE + 4,
   140	 *						struct dfl_fpga_port_dma_unmap)
   141	 *
   142	 * Unmap the dma memory per iova provided by caller.
   143	 * Return: 0 on success, -errno on failure.
   144	 */
   145	struct dfl_fpga_port_dma_unmap {
   146		/* Input */
   147		__u32 argsz;		/* Structure length */
   148		__u32 flags;		/* Zero for now */
   149		__u64 iova;		/* IO virtual address */
   150	};
   151	
   152	#define DFL_FPGA_PORT_DMA_UNMAP		_IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 4)
   153	
   154	/**
   155	 * struct dfl_fpga_irq_set - the argument for DFL_FPGA_XXX_SET_IRQ ioctl.
   156	 *
   157	 * @start: Index of the first irq.
   158	 * @count: The number of eventfd handler.
   159	 * @evtfds: Eventfd handlers.
   160	 */
   161	struct dfl_fpga_irq_set {
   162		__u32 start;
   163		__u32 count;
   164		__s32 evtfds[];
   165	};
   166	
   167	/**
   168	 * DFL_FPGA_PORT_ERR_GET_IRQ_NUM - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 5,
   169	 *								__u32 num_irqs)
   170	 *
   171	 * Get the number of irqs supported by the fpga port error reporting private
   172	 * feature. Currently hardware supports up to 1 irq.
   173	 * Return: 0 on success, -errno on failure.
   174	 */
   175	#define DFL_FPGA_PORT_ERR_GET_IRQ_NUM	_IOR(DFL_FPGA_MAGIC,	\
   176						     DFL_PORT_BASE + 5, __u32)
   177	
   178	/**
   179	 * DFL_FPGA_PORT_ERR_SET_IRQ - _IOW(DFL_FPGA_MAGIC, DFL_PORT_BASE + 6,
   180	 *						struct dfl_fpga_irq_set)
   181	 *
   182	 * Set fpga port error reporting interrupt trigger if evtfds[n] is valid.
   183	 * Unset related interrupt trigger if evtfds[n] is a negative value.
   184	 * Return: 0 on success, -errno on failure.
   185	 */
   186	#define DFL_FPGA_PORT_ERR_SET_IRQ	_IOW(DFL_FPGA_MAGIC,	\
   187						     DFL_PORT_BASE + 6,	\
   188						     struct dfl_fpga_irq_set)
   189	
   190	/**
   191	 * DFL_FPGA_PORT_UINT_GET_IRQ_NUM - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 7,
   192	 *								__u32 num_irqs)
   193	 *
   194	 * Get the number of irqs supported by the fpga AFU interrupt private
   195	 * feature.
   196	 * Return: 0 on success, -errno on failure.
   197	 */
   198	#define DFL_FPGA_PORT_UINT_GET_IRQ_NUM	_IOR(DFL_FPGA_MAGIC,	\
   199						     DFL_PORT_BASE + 7, __u32)
   200	
   201	/**
   202	 * DFL_FPGA_PORT_UINT_SET_IRQ - _IOW(DFL_FPGA_MAGIC, DFL_PORT_BASE + 8,
   203	 *						struct dfl_fpga_irq_set)
   204	 *
   205	 * Set fpga AFU interrupt trigger if evtfds[n] is valid.
   206	 * Unset related interrupt trigger if evtfds[n] is a negative value.
   207	 * Return: 0 on success, -errno on failure.
   208	 */
   209	#define DFL_FPGA_PORT_UINT_SET_IRQ	_IOW(DFL_FPGA_MAGIC,	\
   210						     DFL_PORT_BASE + 8,	\
   211						     struct dfl_fpga_irq_set)
   212	
   213	/* IOCTLs for FME file descriptor */
   214	
   215	/**
   216	 * DFL_FPGA_FME_PORT_PR - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 0,
   217	 *						struct dfl_fpga_fme_port_pr)
   218	 *
   219	 * Driver does Partial Reconfiguration based on Port ID and Buffer (Image)
   220	 * provided by caller.
   221	 * Return: 0 on success, -errno on failure.
   222	 * If DFL_FPGA_FME_PORT_PR returns -EIO, that indicates the HW has detected
   223	 * some errors during PR, under this case, the user can fetch HW error info
   224	 * from the status of FME's fpga manager.
   225	 */
   226	
   227	struct dfl_fpga_fme_port_pr {
   228		/* Input */
   229		__u32 argsz;		/* Structure length */
   230		__u32 flags;		/* Zero for now */
   231		__u32 port_id;
   232		__u32 buffer_size;
   233		__u64 buffer_address;	/* Userspace address to the buffer for PR */
   234	};
   235	
   236	#define DFL_FPGA_FME_PORT_PR	_IO(DFL_FPGA_MAGIC, DFL_FME_BASE + 0)
   237	
   238	/**
   239	 * DFL_FPGA_FME_PORT_RELEASE - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 1,
   240	 *						int port_id)
   241	 *
   242	 * Driver releases the port per Port ID provided by caller.
   243	 * Return: 0 on success, -errno on failure.
   244	 */
   245	#define DFL_FPGA_FME_PORT_RELEASE   _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 1, int)
   246	
   247	/**
   248	 * DFL_FPGA_FME_PORT_ASSIGN - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 2,
   249	 *						int port_id)
   250	 *
   251	 * Driver assigns the port back per Port ID provided by caller.
   252	 * Return: 0 on success, -errno on failure.
   253	 */
   254	#define DFL_FPGA_FME_PORT_ASSIGN     _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 2, int)
   255	
   256	/**
   257	 * DFL_FPGA_FME_ERR_GET_IRQ_NUM - _IOR(DFL_FPGA_MAGIC, DFL_FME_BASE + 3,
   258	 *							__u32 num_irqs)
   259	 *
   260	 * Get the number of irqs supported by the fpga fme error reporting private
   261	 * feature. Currently hardware supports up to 1 irq.
   262	 * Return: 0 on success, -errno on failure.
   263	 */
   264	#define DFL_FPGA_FME_ERR_GET_IRQ_NUM	_IOR(DFL_FPGA_MAGIC,	\
   265						     DFL_FME_BASE + 3, __u32)
   266	
   267	/**
   268	 * DFL_FPGA_FME_ERR_SET_IRQ - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 4,
   269	 *						struct dfl_fpga_irq_set)
   270	 *
   271	 * Set fpga fme error reporting interrupt trigger if evtfds[n] is valid.
   272	 * Unset related interrupt trigger if evtfds[n] is a negative value.
   273	 * Return: 0 on success, -errno on failure.
   274	 */
   275	#define DFL_FPGA_FME_ERR_SET_IRQ	_IOW(DFL_FPGA_MAGIC,	\
   276						     DFL_FME_BASE + 4,	\
   277						     struct dfl_fpga_irq_set)
   278	
   279	#endif /* _LINUX_FPGA_DFL_H */