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The C and C++ Include Header Files

/usr/include/ntirpc/rpc/rpc_cksum.h


$ cat -n /usr/include/ntirpc/rpc/rpc_cksum.h

     1	/*-
     2	 *  COPYRIGHT (C) 1986 Gary S. Brown.  You may use this program, or
     3	 *  code or tables extracted from it, as desired without restriction.
     4	 */
     5	
     6	/*
     7	 *  First, the polynomial itself and its table of feedback terms.  The
     8	 *  polynomial is
     9	 *  X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0
    10	 *
    11	 *  Note that we take it "backwards" and put the highest-order term in
    12	 *  the lowest-order bit.  The X^32 term is "implied"; the LSB is the
    13	 *  X^31 term, etc.  The X^0 term (usually shown as "+1") results in
    14	 *  the MSB being 1
    15	 *
    16	 *  Note that the usual hardware shift register implementation, which
    17	 *  is what we're using (we're merely optimizing it by doing eight-bit
    18	 *  chunks at a time) shifts bits into the lowest-order term.  In our
    19	 *  implementation, that means shifting towards the right.  Why do we
    20	 *  do it this way?  Because the calculated CRC must be transmitted in
    21	 *  order from highest-order term to lowest-order term.  UARTs transmit
    22	 *  characters in order from LSB to MSB.  By storing the CRC this way
    23	 *  we hand it to the UART in the order low-byte to high-byte; the UART
    24	 *  sends each low-bit to hight-bit; and the result is transmission bit
    25	 *  by bit from highest- to lowest-order term without requiring any bit
    26	 *  shuffling on our part.  Reception works similarly
    27	 *
    28	 *  The feedback terms table consists of 256, 32-bit entries.  Notes
    29	 *
    30	 *      The table can be generated at runtime if desired; code to do so
    31	 *      is shown later.  It might not be obvious, but the feedback
    32	 *      terms simply represent the results of eight shift/xor opera
    33	 *      tions for all combinations of data and CRC register values
    34	 *
    35	 *      The values must be right-shifted by eight bits by the "updcrc
    36	 *      logic; the shift must be unsigned (bring in zeroes).  On some
    37	 *      hardware you could probably optimize the shift in assembler by
    38	 *      using byte-swap instructions
    39	 *      polynomial $edb88320
    40	 *
    41	 *
    42	 * CRC32 code derived from work by Gary S. Brown.
    43	 */
    44	
    45	#ifndef RPC_CKSUM_H
    46	#define RPC_CKSUM_H
    47	
    48	/* table-driven, software crc32c */
    49	uint32_t calculate_crc32c(uint32_t crc32c, const unsigned char *buffer,
    50				  unsigned int length);
    51	
    52	#endif				/* RPC_CKSUM_H */